An Efficient 16nm Fin-FET Memory Testable System Design And Analysis

With the improvement and perfection of IC manufacturing technology,the SOC integration is getting higher and higher,and the proportion of embedded memory in SOC is also increasing.However,complex new processes are also more likely to lead to new defects in the production of the memory,which in turn lead to new failures of the memory.As a result,memory testing becomes increasingly difficult.Because of its advantages of simple design,moderate hardware cost and high fault coverage,the built-in self-test method has become the mainstream memory test method.Memory testing algorithm is the core of MBIST circuit,and March algorithm is the most widely used memory testing algorithm nowadays.Commonly used March algorithms,such as March C,March C+,etc.,only aim at static fault testing,but after Fin-FET process,researchers find that Fin-FET memory is more sensitive to dynamic fault,so dynamic fault testing has become a problem that can not be ignored.This paper mainly studies the built-in self-test system of 16 nm Fin-FET memory.The main work is as follows:(1)The principle of static and dynamic faults of memory is studied,and the principle of common memory testing algorithms and fault coverage are analyzed.In view of the fact that Fin-FET memory is more sensitive to dynamic faults,an improved dynamic fault testing algorithm is proposed.The coverage of dynamic faults of single memory cell with two sensitization operations is 100%with the improved algorithm and the March MDIa and March MDIb algorithms,but the complexity is reduced by about 24%compared with the two algorithms.(2)An MBIST circuit with four test algorithms is designed.When testing,only one test algorithm or four algorithms can be executed sequentially according to the requirements.Then through NC-Verilog,the RTL level simulation of MBIST circuit is completed.(3)First,the logic synthesis and formal verification of MBIST circuit are completed by EDA tools.Then,the layout and wiring of test chip are completed through back-end physical design.Finally,the GDS ? layout file of test chip is obtained.