Research On Decoding Algorithms And The Implement Of LDPC Codes Based On The CMMB Standard

Low-Density Parity-Check (LDPC) codes are a class of linear block codes. A LDPC code isspecified for its parity-check matrix which is a sparse matrix that most elements in it are zeroelements. LDPC codes are another kind of good codes that can provide near capacity performancefollowing Turbo codes. Besides this, LDPC codes have other advantages comparing with Turbo codes.Over all, LDPC codes became an important topic in error-correcting codes. The coding and decodingalgorithms and the implementation have always been concerned.This thesis bases on the LDPC code in CMMB (China Mobile Multimedia Broadcasting)standard and aims at implementing an LDPC decoder in FPGA. Firstly, a systematic study of LDPCcodes especially the LDPC code in CMMB is made. In the next, the analysis and simulation of severaliterative LDPC decoding algorithms are carried out. We find modified min-sum algorithms cantremendously reduce the computational complexity, while keeping the performance. Finally wechoose normalized min-sum algorithm as our decoding algorithm for implementation.On these bases, the hardware implementation of the LDPC code in CMMB is researched.Through the further simulation, the quantization method, the maximum iteration number and thenormalized coefficient are fixed. The overall structure of the decoder is designed. The key modulesand the storage of data are deeply researched. The design diagrams of the modules are given.At the end of the thesis, we describe the FPGA techniques including the development and designmethod. The selection of devices is also studied. We implement a (3,6) regular LDPC decoder withlength20using Verilog Hardware Description Language and apply the function simulation. Thecreated symbol and simulation waveform are given. The simulation result proves the validity of thedesign.