The SAR Imaging System Based On Fast Processing

As the higher request of the synthetic aperture radar(SAR) image quality, the design of high performance real-time processing system become more and more important. The data volume and huge computation task of SAR is concentrate on rangeand azimuth compressions——the basic computation of which is FFT. The usualmeasure of compression is using parallel high speed DSPs, which was considered as the best way of real-time SAR processing in hardware, but it should use distributed algorithm and complicated control, further more, it just can be applicable for the small points FFT. The programmable chips-FPGA technique is improving so fast that it has become a better way to realize compression than DSP.This dissertation discussed a very effective blue print and designed a high performance FFT processor based on the new platform. The design adopts the more effective algorithm of radix-4 and decimation-in-time(DIT) compared with other fast fourier transform algorithm. In the course of realization, the pipeline structure, symmetric Dual-RAM and optimum parallel operation butterfly are adopted, which can make butterfly of every stage compute at the same time, and make the module extend easily. In the aspect of data precision, the block float point arithmetic operations are adopted to balance the contradictory between the speed and precision. Especially, the CORDIC algorithm is used to make twiddle factor dynamically, which don't need largenumbers of ROM utilizations for the complicated and inextensible way——Look-UpTable(LUT).In a word, this design had been up to a new level in the significant factors of real-time, precision and utilizations, which is based on the abundant resources and new project. Furthermore, it is simulated and verified, which is valuable in military and civil application.