Software/Hardware Co-Design Of AVS And H.264 Unified Decoder Based On ESL Methodology

As the complexity of SoC design increases, system-level design in early development stage is imposing ever more influence on the final SoC performance. It is necessary to optimize the performance on the architecture level of a video decoding SoC with a highly effective analysis and verification platform. In the SoC design process, software and hardware co-simulation is a must, since SoC platform consists of both hardware partitions and software partitions.It is fairly difficult to find the performance bottleneck of the system at the RTL levels, since the performance verification only occurs towards the back end of the whole design flow. Therefore, a new methodology of system level design is required to explore in the architecture design space given the high complexity of video decoding SoC as well as the need to make a decision on the software and hardware parttion at early stages in design flow.The thesis presents an Electronic System Level design methodology for hardware and software Co-Design of AVS&H.264 decoding SoC. We make the HW/SW partition after analyzing the software algorithm bottlenecks of AVS&H.264 on the ESL platform. Based on the previous work, we establish an AVS&H.264 unified decoder on the ESL platform. The thesis focuses on the hardware modeling of IDCT of the unified decoder. During the modeling, we present a kind of reasonable hardware architecture of IDCT algorithm together with the shared mechanism between AVS&H.264 in the model. The results of HW/SW co-simulation show that the model can accelerate the decoding speed greatly.Software/Hardware Co-simulation of AVS&H.264 Decoding SoC is implemented. It is shown with strong confidence that ESL Design is not only helpful to analyze the system performance in the early developing period but also can accelerate the simulation speed.