Research On The Embedded SoC Hardware Architecture For Gaze Estimation Algorithm

Gaze estimation is a studying focus in the field of image processing and pattern recognition. It plays a very important role in applications concerning natural interaction between man and machine. Based on the hardware/software co-design methodology, this thesis designs a SoC hardware architecture for the algorithm of gaze estimation on the basis of previous research work, and some important design issues are also discussed.The objective of investigation is to propose a new algorithm of gaze estimation with high accuracy, and study the real-time implementation approaches. We first locate face area and eyes feature points in a single frame obtained from video camera, and then estimate gaze direction and fixation point with the consideration of face inclination, pupil and inner-canthus.Face detection is the most complicated part of the gaze estimation. For the performance bottleneck of AdaBoost algorithm running on the embedded platform, an embedded configurable high performance processor (NiosⅡ) can take charge of task scheduling and a small amount of computing tasks, and dedicated hardware accelerators are designed to deal with data intensive computing tasks through multi-level parallelism to meet the real-time requirement in embedded applications. In addition, this thesis will further discuss the hardware architecture, and bring the configurable and extensible processor into full play to design a prototype system.The architecture is prototyped on Altera CycloneⅡFPGA. The evaluation result shows that the system performs real-time detection with low resource consumption and high detection rate. The detection speed of image consisting 640×480 pixels is 12 frames/s, and 41 frames/s for image consisting 320×240 pixels. It meets the requirement of gaze estimation.