AVS Decoding SoC Design And Hardware Implementation Of Intra Prediction Based On ESL Design

As the complexity of SoC design increases, system-level design in early development stage is imposing ever more influence on the final SoC performance. It is necessary to optimize the performance on the architecture level of a video decoding SoC with a highly effective developing platform. In the SoC design process, software and hardware co-simulation is a must, since SoC platform consists of both hardware partitions and software partitions.It is fairly difficult to find the performance bottleneck of the system at the RTL level, since the performance verification only occurs at the end of the whole design flow. Therefore, a new methodology of system level design is required to explore in the architecture design space given the high complexity of video decoding SoC as well as the need to make a decision on the software and hardware partition at the early stage in the design flow.The thesis presents an Electronic System Level design methodology for hardware and software Co-Design of AVS decoding SoC. In the thesis, the HW/SW partition is made after analyzing the software algorithm bottlenecks of AVS decoder on the ESL platform. The thesis focuses on the hardware modeling of intra prediction algorithm in the decoder. In the modeling, we make reconfigurable design of AVS intra prediction algorithm and present a kind of reasonable hardware architecture. The results of HW/SW co-simulation show that the fuction of the model is right and the model can accelerate the decoding speed greatly. We do the hardware implementation of intra prediction by Verilog-HDL and make synthesis of the hardware model on the FPGA.Hardware/Software Co-simulation of AVS Decoding SoC is implemented. It is shown with strong confidence that ESL Design is not only helpful to analyze the system performance in the early developing stage but also can accelerate the simulation speed.