GrC-Based Research On Rapid Optimization Algorithms For Sequential Logic Circuits

The optimization of logic circuits is one of the core issues in the analysis and design of large-scale integrated circuits.One of the tasks of the optimization of sequential logic circuits is state reduction,that is,under the premise of guaranteeing the circuit design requirements,the state set with the same logic relationship in the sequential logic system is found,and the purpose of reduct the logic circuit is achieved through the merging of the states.With the increasing complexity of logic circuit design,the state reduction of sequential logic circuits poses great challenges.As an artificial intelligence method that can deal with massive data and uncertain information,granular computing has received extensive attention in recent years.This paper attempts to effectively combine granular computing theory with the state reduction of sequential logic circuits.For state reduction of the completely specified sequential logic circuit,the output matrix and the sub-state matrix are defined first,and then the system matrix formed by the fusion of the initial state marker matrix and the labeled sub-state matrix is defined.The system matrix can completely reflect the output and sub-states of the circuit system.Based on the equivalence relation model in granular computing,the final maximum equivalence class set can be obtained by finding the same column of the system matrix.Price status,complete status simplification.The algorithm process avoids the matrix multiplication operation and the intersection between equivalence classes.The efficiency of simplification is greatly improved.For state reduction of incompletely specified sequential logic circuits,the state particles are first marked,the maximal compatible class set is obtained based on the compatible relation model in granular computing,and then the initial state tree is constructed based on the "key" compatible class to obtain all the minimal coverage;the minimum state tree is finally constructed to verify the closure of the minimum coverage.If all the minimum coverages are not closed,the optimal results can be obtained through the minimum coverage tree.Finally,a system platform for the state reductio of sequential logic circuits is designed,and different algorithms are integrated for both circuits.We also summarize and look forward to the next research direction.