Research On Execution Mechanism Of Hardware Thread For CPU/FPGA Hybrid Architecture

CPU/FPGA hybrid architecture combined with CPU and FPGA is a common form of Reconfigurable Computing(RC), which can provide a higher level parallel of computing power flexibly. However, as for RC platform, operating system supports is still not sufficient, there are two difficulties which prevents RC from being widely used. The first difficulty is that the design method of RC is still too complex to generate hardware configuration automatically. The second difficulty is that the communication of reconfigurable applications and the CPU application imposes significant overhead.In order to resolve these problem and to improve the performance efficiently with RC, this paper presents a hardware thread model on CPU/FPGA hybrid architecture with Scratch-Pad memory as storage for shared data. The hardware thread can be used to support the compute-intensive task with true parallelism while keep the flexibility of software control. The hardware threads presented in this paper can be compiled from high level programming language such as C to hardware description language through Handel-C compiler or make use of the existing optimized VHDL logic algorithm. This method simplifies the design process from software to hardware and provides the chance of program execution by hardware.In this paper, we use Simics simulation platform with a simulated 256KB of Scratch-Pad memory, 3M logic gates of reconfigurable hardware and a general processor as the evaluation platform. DES, MD5SUM and MergeSort algorithms are performed on this platform. The results shows that the speedup of program execution on this model is 2.14 in average and the decrease of memory miss rate is 73.3%.It shows that hybrid threading model with SPM as shared data storage can take use of the performance advantages of hybrid architecture without loss of data access speed.