Design And Application Of Low Jitter Phase Locked Loop

Low phase jitter is required to achieving high performance of PLL. The reason of jitter generation is analyzed, and a low phase jitter of PLL is described, which is used in USB1.1 transceiver. Main block inside PLL, including LPF and VCO, is addressed. SPICE simulation shows that PLL can generate 96MHz clock with 12MHz reference clock, whose jitter is about 800ps. And the simulation result indicates that the thesis meets the demand of desired specification.