Research On Synthetic Aperture Radar Image Processing Hardware Accelerator

Synthetic aperture radar has wide application in military and national economy and develops towards multi-wave band,multi-polarity,high width and high resolution.This tendency will exert more demand in real-time SAR image processing.Therefore,this paper has a deep research on two key aspects in the design of SAR image processing hardware accelerator—data access and data processing,and proposes optimization solutions respectively.It is necessary to have intercross access of row and column of data matrix in the Chirp Scaling(CS) algorithm and two-dimension discrete wavelet transform(2D-DWT) in the SAR image processing.But there is a big difference between the speed of row access and column access due to the trait of SDRAM.As a result,data access becomes the bottleneck of SAR image processing.Therefore,we propose a data matrix layout scheme and the optimal window access theory to balance the speed of row access and column access of data matrix,and achieve the optimization average bandwidth,according to the access law of CS algorithm and the trait of burst access oriented and multi-bank structure of SDRAM.Then we design and implement a SDRAM controller based on the mode of window access to solve the problem of data matrix access in the CS algorithm.According to the research of 2D-DWT,a multiple parallel scheme with 2×2 processor array is used to speed up 2D-DWT.In order to enhance the memory bandwidth to match the computation bandwidth of processor array and increase its utilization,we optimize the storage organization through multi-level buffer memory and dual SDRAM storage structure,which employ theory of pingpong operation and invalid data reusing.Finally,a multi-level 2D-DWT is implemented based on the above design.This paper studies the design of rapid and high-precision data processing module to resolve the problem of data processing in the SAR image processing.In the design of FFT-PE module, the most important component among SAR image processing,we uses FFT module to accomplish IFFT operation,and reuses the floating-point functions modules to design dynamic resuable pipeline structure to save hardware resources.For the calculation of several transcendental functions in the SAR image processing,this paper also makes a research on the CORDIC algorithm and proposes a parallel CORDIC algorithm,which uses sign-predicted and CORDIC iteration expansion methods,to implement an efficient trigonometric function.At the same time,we propose a hybrid mode CORDIC algorithm and design a CORDIC floating-point co-processor to calculate several transcendental functions to meet the required speed and precision of SAR image processing.Finally,we implement a rapid high-precision SAR image processing hardware accelerator on FPGA based on the above optimization methods.Experiments show that these methods have well solved the problems of data access and data processing.