GNSS Receiver CMOS RF Front-End Integrated Chip System Level Design

Global Navigation Satellite System (GNSS) - represented especially by Global Positioning System (GPS) - application industry has been gradually becoming as a global, multi-area high-tech industry. Expansion of GNSS application areas and enlargement of the market continue to expand the need for GNSS receiver. Radio frequency (RF) front-end integrated chip is one of critical components for GNSS receiver. Its design and industrialization are important for establishing a complete and perfect GNSS industry chain of our country.In this thesis, system level design for GPS receiver RF front-end integrated chip as an example has been discussed. RF front-end's primary functions are the amplification, mixing, filtering and sampling for the weak signal from the GPS receiver antenna to get the appropriate intermediate frequency signal used in the baseband chips. Different from other wireless communication systems, GPS receiver requirements are not well defined yet. So the system level design for GPS receiver RF front-end integrated chip is important for GPS terminal design and RF/Analog circuits design.In this thesis, the main objective is to identify a universal, low-power, and high integrated GNSS receiver RF front-end chip architecture. Based on the analysis and study for the GPS system, the signal spectrum characteristics of received GPS signal on the earth and correlated signal needed by the baseband chip, the GPS receiver front-end architecture has been designed. Low-IF receiver architecture with intermediate frequency of 4.092MHz has been chosen. The specifications for the front-end chip also been defined, including the maximum gain, gain dynamic range, noise figure, sensitivity, image rejection, filter characteristic, phase noise, and ADC bit resolution. Based on the performance of the overall front-end chip, specifications of the circuit blocks have been defined. In the IF section, identifying the image rejection block realized by 2 stage RC passive polyphase filter with 20dB image rejection ration (IMRR) in 2MHz bandwidth. In this thesis, the system level simulation of the front-end architecture and specification are also designed with ADS.