.315 Mhz, Cmos Wireless Receiver Chip Rf Front-end Circuit Design And Layout To Achieve

With the great developments and demands on wireless communication technolog-ies, low power dissipation, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver's front-end circuit-s play an important role in achieving its excellent performances.FSK is a ISM/SRD short-range wireless technology, which is used early and wid-ely. This thesis researches the front-end circuits of the 315MHz FSK receiver, includ-ing a low noise amplifier(LNA), a mixer and a image-rejection filter. These radio fr-equency circuits are designed and implemented using the chartered 0.35μm CMOS technology.The proposed LNA is a single-ended narrow-band cascade amplifier with inductive source degeneration, which is designed mainly using power-constrained simultaneous noise and input matching technique named PCSNIM, in addition, some other measures are taken to improve the circuit performances further. The mixer adopts quadrature image-rejection structure in order to increase IRR, and the mixer units adopts modified double balanced Gilbert cell in order to increase the port-to-port isolation and reject common-mode noise. The image-rejection function is achieved by a four-stage p-olyphase filter with high IRR on chip.Simulation results show that the front-end draws 2.18mA current from a 3.3 V power supply, has a 34.54dB noise figure, and a voltage gain of 55.07 dB and-39.84 dBmⅡP3.