Cmmb Tuner Cmos Rf Front-end Design

Due to its convenience in wireless receiving and richness in TV contents, digital multimedia broadcasting has been receiving extensive attention in multiple areas around the world. China Mo-bile Multimedia Broadcasting (CMMB), as the digital multimedia broadcasting standard in China, is formally proposed in 2006 by the State Administration for Radio, Film and TV. A single chip im-plementation of the tuner with the lowest cost is the best option oriented to receive CMMB signal. This thesis deals with the Radio Frequency (RF) front end of the receiver, which is an important part for the fully integrated single-chip solution of CMMB tuner.Several popular receiver architectures are firstly introduced and compared. A Zero-IF receiver architecture is chosen as the solution to this problem. System requirements of the receiver are dis-cussed. The noise and linearity requirements for the whole system and each block of system are calculated according to the specific communication standards.In the RF front end of the receiver, Low Noise Amplifier (LNA) and Mixer are two critical modules. Design issues such as input impedance matching and noise optimization of LNA are cov-ered. To be compatible with other similar standards such as DVB-H in Europe, T-DMB in Korea and even FM radio, there're three LNAs in parallel to cover the three bands respectively, i.e.80～245MHz,470～860MHz,1.452～1.492GHz. Each of these LNAs has two gain modes to balance the noise and linearity specifications.To accommodate to the large dynamic range of input signals and high sensitivity requirements of the system, three stages of Radio Frequency Programmable Gain Amplifier (RFPGA) are inter-posed between the LNAs and the Mixer. Since the LNA output is single ended signal whereas dif-ferential signal is preferred on chip, the first stage RFPGA realizes the active balun (BALanced to Unbalanced) conversion function. A Multiple Gated Transistor (MGTR) structure is introduced to improve the linearity in the second stage RFPGA while the third stage RFPGA improves the preci-sion of gain step.The flicker noise and linearity of mixer are also discussed and a passive mixer structure is cho-sen. The circuit is carefully analyzed and designed. Besides, the simulation results are given.To tune the gain of LNAs and RFPGA dynamically, a Radio Frequency Received Signal Strength Indicator (RFRSSI) circuit and gain control loop are adopted to try to settle down the sig-nal power at the input of mixer.All the above blocks are designed and fabricated in UMC 0.18μm RF technology and packaged in QFN40. The simulation and verification results are presented.