Design And Realization Of FPGA-based Digital Video Capturing System

This dissertation gives details on how to improve the real-time image tracking system. And propose and design a digital video capturing system based on FPGA to convert analog video signals into digital video signals, which can be used as the digital video resource to the real-time image tracking system.The design of real-time image tracking system based on uncooled staring IR focal plane array has space to be improved. The Stratix series FPGA EP1S10 which is high-end FPGA series of Altera Corporation was used but not fully used. Two external dual-port RAMs were used in the design although EP1S10 has large-volume On-Chip memory that can be utilized. Thus, it did not only waste the resource, but also make it hard to route PCB. So it is easy to draw the conclusion that replacing the dual-port RAM on the FPGA-board with FPGA's On-Chip memory can not only save a dual-port RAM to cut the cost, but also ease the PCB routing. This dissertation analyzes the feasibility of the improvement in aspects of memory volume and timing.When debugging the real-time image tracking system boards, the IR focal plane must be provided so that there are digital video resources for the system to process. Since the IR focal plane is expensive, there is only sequence scene transmitter to provide digital image resources in the lab now. But the sequence scene transmitter is lack of flexibility for that it can only provide sequence image stored in the PC. So if we can design a digital video capturing system which can convert analog video signals into digital video signals for subsequent image processing, it has several advantages. First of all, it can offer another image sources besides IR focal plane and sequence scene transmitter, secondly, it gives more flexible image resource, and thirdly, it can reduce the cost. This dissertation gives details on how this system is designed and realized. The system is based on EP1C6Q240 which is Cyclone series of Altera Corporation and ADV7183B which is a video decoder of ADI Corporation. I~2C bus is required to control the ADV7183B. In this system, the I~2C bus function is realized in two ways: Verilog HDL and Nios II which is a very popular soft-core, moreover, the concept IP Core is first introduced in the Nios II system. These two methods have been compared based on the result. In this paper, I discuss in details what the watch-dog is and how the watch-dog circuit is designed as well. Meanwhile, I introduce a new debugging method, using Embedded Logic Analyzer (ELA)-SignalTap II instead of the expensive Logic Analyzer. I also explain what the analog and digital videos are. This dissertation is summed up in a few words and several improvements have been proposed for the future research.