The Algorithm Structure Research And Optimization Design Of Fixed-point Arithmetic Units

In the field of IC design, microprocessor is the core part of a digital system due to which the requirement for its performance becomes higher and higher. The powerful operation ability comes from its internal arithmetic units, so it's of great value to design these units with high performance. Among most kinds of processors, adder is the most fundamental arithmetic component since addition is the most often used operation, while multiplier plays a key role in today's modern microprocessors and digital signal processors.This paper focuses on the optimization of algorithm and logic circuit design of integer adder and multiplier. Based on the optimized parallel-prefix formulation, Ling carry and modified carry-select module, a new adder is presented. In the design of high-performance multiplier, a kind of select-logic partial product generating unit is employed. What's more, the design and realization of high order compressors 6:2 and 9:2 are completed by researching the partial product compressing array. Through optimizing the multiplier topology, this paper implemented three improved parallel multipliers and a four-cycle serial-parallel multiplier.The whole design is described with Verilog HDL. The results of synthesis and simulation based on FPGA show that the new adder and the modified multipliers all have better performance compared with those using traditional methods.