Studyand Hardware Implementation Of The Deblocking Filter Algorithm In Video Stream

In the recent 10 years, the multimedia video are developed very quickly with the quick development of network video stream and with the increasing popularity of digital TV. On the other hand, video encoder technology has been improved significantly and applied widely.Nowadays,as lots of video stream encoder and decoder standards are used worldwidely, H.164/AVC and AVS are almost the top two standards in the area of compression and encoder efficiency. The compression efficiency of H.264/AVC standard is about two times of that of MPEG-4. Under the condition of bandwidth less than 1M, H.264/AVC standard can achieve the imaging quality of DVD, and be suitable for network video transmission. AVS is a project towards to an open and cost-efficient Chinese national standard. Its applications are very popolar such as HDTV, high-quality digital broadcast, IPTV, digital multimedia, etc. It is best suitable in China as a result of its high-quality, low-complexity, low-price, and simple to license the package of all central patents in low price, etc.The blocking artifacts can occur from block-based processing, such as block-based prediction, motion compensation, transformation, quantization and its inverse process in video stream encoding and decoding system. Therefore, adopting deblocking loop filter can remove these blocking artifacts and achieve much better subjective and objective visual quality and to degrade the distortion in the boundaries of blocks. It can also decrease the accumulation errors between frames.The algorithm of video stream deblocking filter is deeply studied in this paper. The efficient VLSI architectures are proposed for the deblocking filter. Filtering order and memory layout are carefully designed to optimize the processing speed and on-chip memory cost. The performance and cost of each architecture was systematically discussed. For H.264/AVC decoder, this deblocking algorithm is implemented by ASIC flow(UMC 0.18um CMOS Technology). But for AVS decoder, we use FPGA flow to synthesize and verify the hardware architecture of deblocking filter.This paper proposed the deblocking loop filter system in H.264/AVC and AVS decoder. From the result of simulation, the deblocking filter system in H.264/AVC can easily achieve the real-time deblocking of High-definition TV video application(1920×1088@29Hz;1280×720@66Hz) ) when worked at 100MHz, but for AVS, only when worked at 35MHz, the system can support the real-time deblocking of HDTV video application(1920×1088@43Hz).