Research And Implementation Of Deblocking Algorithm In Video Processing System

Most of the current video encoding and decoding compression standards such as H.264, MPEG-4 and AVS are based on BDCT (Blocked Discrete Cosine Transformation). However, this is a method that dividing the image into blocks and independently processing each block. Its biggest disadvantage is that it will cause blocking effect in low bit rate. Thus it is necessary to include deblocking filter in the whole video system.Deblocking filter can be divided into two types: in-loop filter and post filter. H.264 and AVS have both defined the in-loop deblocking algorithm to increase the quality of motion estimate. However, it doesn't concern much about subjective visual effect. Thus post deblocking filter should be added to video systems to increase subjective visual effect even if in-loop filter is included. On the other hand, compared with in-loop filter, post filter is more general and has been widely used. This thesis mainly focuses on the research and implementation of deblocking algorithm in video processing system. The paper first introduces the generation of blocking effect, the classification of deblocking filter and human visual system. Then in-loop and post filter is introduced in detail.Based on the feature of human visual system, the paper does research and many experiences on the mode, parameter and mode decision method of current post deblocking algorithm to make some improvements. All these are aimed at improving subjective visual effect and decreasing complexity in realization. Using Matlab to observe the result and it shows that the improved algorithm also has good effect while providing the academic basis of decreasing the cost of implementation.Based on the research, the proposed algorithm is implemented in the paper by hardware accelerator in RTL level and synthesizes it using 0.18um TSMC technical library. It is shown in the results that the proposed algorithm and hardware architecture can meet the real-time processing requirement using less memory. Since the hardware accelerator is not flexible, the paper using MOVE processor to realize the algorithm and making advantage of its high compatibility and strong scalability. By doing this, its flexibility is improved while ensuring the speed and performance.