Research On PIC12F509 I_DDA Testing And Self-feedback Testing

IC(Integrated Circuit) testing technology is the key of producing high- performance IC and improving finished IC product rate.With the development of IC technology,voltage testing and IDDQ testing can not satisfy test requirement of high-performance IC. IDDT testing,which was proposed in middle 1990's,can detect certain faults that can not be detected by traditional test methods,but its severe demand on test equipment made it still in the research stage.Directing at the present situation that IDDT testing depends on test equipment,Professor Min Yinhua and some other researchers in Chinese Academy of Sciences proposed IDDA testing.The feasibility of this testing method has been proven by simulation experiment,but it still needs practical test experiment.This paper applies instruction level At-speed current testing to PIC12F509 microprocessor, with the hope of proving the feasibility of IDDA testing through practical experiment.The instruction level At-speed test of PIC12F509 takes compile testing program as test vector, proposes a test strategy aiming at testing paths on the basis of a detailed analysis of PIC12F509 and presents a method of producing test program. Experimental results show that using instruction level At-speed test method to PIC12F509 microprocessor is feasible.By testing all the data paths,the faults of data path,as well as data transfer faults caused by control faults, can be detected.The method of random test based on self-feedback can generate test vectors simply and save the spending of memory for storing test vectors,but it needs fault simulation to every test set to find high fault-coverage test set,which is quite time consuming.In order to reduce the number of fault simulation times and fault simulation time,a self-feedback random test method based on hamming distance is proposed.By discussing the relationship between hamming distance of test sets and fault coverage,the interval range of hamming distance that corresponds to high fault coverage test sets is found. the number of fault simulation times and fault simulation time can be reduced by executing fault simulation only on the test sets in such interval range.