The Study Of FSG Etching In No-stop-layer Dual Damascene Structure

Together with the continuous growing of IC industry and scaling down of feature sizes, copper has been proven to be a good candidate as interconnect material. However, it is difficult to etch copper due to the existence of nonvolatile by-products. Dual-damascene technology has thus been developed to overcome the drawback mentioned above. This paper reviews our recent work on FSG etching in the no-stop-layer dual-damascene technology. The removal of stop layer reduces the whole chip dielectric constant K, and thus improves the chip performance by reducing RC delay.The whole etching process consists of four steps: VIA Etch, BARC Etch, Trench Etch and Nitride Remove. Each etch step was analyzed through a lot of experiments in order to solve issues encountered during etching. The primary issues during each step were also discussed in details. The issues and the solutions developed during this research are also helpful to improve other VLSI manufacturing processes.