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Technology Research And Development For 55nm Metal Hard Mask All-in-one Etch Process

Posted on:2017-10-19Degree:MasterType:Thesis
Country:ChinaCandidate:K Q AngFull Text:PDF
GTID:2428330590490295Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
By the decreasing of critical dimension of VLSI(Very Large Scale Integration),Dual Damascenes Cu interconnection is widely used in BEOL integration schematic while Metal Hard Mask All-In-One etch is the most advanced technique till now.Compared to PR mask approach,MHM AIO Etch is good at CD control,process expansibility and less low-k damage;but TiN hard mask brings side effect in process control as well.This paper described the issues and solutions during the development of a 55 nm MHM AIO(Metal Hard mask All-In-One)etch process: find the high selectivity condition thru DOE(Design of Experiment),solved the over etch of TiN hard mask as well as the surface residue issue;reduced the by-production generated residue defect by optimizing both etch pre-condition and transition between process steps.The Optimized Process Physical window was verified: Low-k over etch>30% and SiCN over etch~100% for via structures,significant over etch amount has been achieved.;Process Electrical window was verified as well: both metal Rs and via Rc are within specification when all step time ±10%,yield no degradation under both conditions;EM Reliability test result shows the life time is 89.5years(SPEC is >10years).Finally the optimized process met the electrical,yield and reliability requirements and improved the performance of massive productions.
Keywords/Search Tags:Dual Damascene Schematic, Low-k Dielectric Material, Metal Hard Mask All-In-One Etch, Over Etch, Block Etch, Polymer Residue, Defect
PDF Full Text Request
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