The Rearch And Implementation Of Load Balance Technique For Network Processor

Now the growth of the network processor speed can not keep up with the growth ofuser traffic and link bandwidth, so adopting the parallel architecture can efficientlyimprove the network processor performance. Parallel network processor is comprised ofmultiple processing elements(PE), coprocessors and hardware logic blocks(HLB). Thereexist many parallel modes among PEs and between PE and coprocessor, whichsufficiency brings into play the characteristic of network processor such asprogrammable and expansible.Load balance is the key to improving the throughput of network processor.Unfortunately, load balance may cause packet reordering, which will unnecessarilytrigger the TCP congestion control mechanism, and thus deteriorate the performance ofTCP connections and the network utility. How to deal with the contradiction is a bigproblem in network processor design.This thesis studies currently in common using load balance arithmetic and pointsout the adaptive highest random weight (AHRW) arithmetic. AHRW has the propertiesof packet ordering, low overhead, minimal disruption and can dynamicly adjust loadbalancing based of current status. What's more, this thesis studies network trafficcharacteristics, then provides flow classifier scheduling scheme that classifies Internetflows into two categories: the aggressive and the normal, and applies differentscheduling policies to the two classes of flows. When the system is in balanced state,packets is assigned according to the AHRW arithmetic. When system is unbalanced,the load adapter will adjust the aggressive flow, the normal flow will be assignedaccording to AHRW arithmetic still. This can guarantee load balancing and reduceadaptation disruption. To validate the performance of the scheme, we designed a packetparallel scheduling simulator FES, which combines the Internet true trace drive anddummy clock advancing. At last, we analysis the performance of many sorts ofarithmetic from load balancing degree, packet loss rate, adaptation disruption, andpacket reordering, the result is: AHRW has better performance compareing with otherarithmetic.At last, this thesis designs a 10G interface in a core router using AHRW arithmetic,and brings forward a method of how to implement a high speed parallel forward systemusing 3 IBM NP4GS3 low speed network processors, realizing high speed packetforwarding. In this thesis, we particularly introduce how to design the packet parallelforward module, which is the kernel of the 10Gbps high speed parallel forward system.