Research On Some Key Techniques In The Design Of Network Processors

With the development of network applications, network devices need more intelligent processing capability. This requires network devices to have various functions (e.g. multi-layer switching, security processing and traffic management) as well as powerful protocol processing capability and programmability, so that the novel network services can be quickly deployed and configured in these network devices. Thus network processors (NPs) which are based on the technology of Application Specific Instruction Processor (ASIP) emerge timely and are widely used in network domains to meet these requirements. NPs have already become one of the core devices in the next-generation Internet.This dissertation focuses on the issues of system design and implementation of NPs. The early design method and performance evaluation of NPs are presented on the standpoint of system design, and several key implementation technologies of NPs are investigated in-depth in this dissertation. The main contributions of the dissertation are as follows:(1) Aiming at the optimal decision and performance evaluation of system design in NPs, the YinHe Network Processor Design Framework (YH-NPDF) is constructed according to the characterization of Multi-Processor System on Chip (MPSoC) design and requirements of network packet processing. The YH-NPDF is based on the idea of platform-based design. It adopts the Reactive Dataflow Process Network (RDPN) model to describe network applications and establishes the parameterized model of NPs' hardware resources, where application model is mapped into the parameterized architecture model of NPs to evaluate the NP performance. The global annealing genetic algorithm is used to accelerate the search of design space and to optimize the design decision of NP system. The YH-NPDF can be used to model network applications and hardware resources and support optimal decision to meet the requirements for intelligent packet processing in early system design of NPs.(2) In network processors based on parallel processing elements (PEs), a packet parallel scheduling algorithm based on Fuzzy Feedback Control Loop (F2CL) is proposed. This algorithm uses F2CL schemes to improve the degree of load balancing among multiple processing elements, and also deploys a flow cache to buffer the scheduling information of packet streams. The packet reordering is effectively controlled by using the following two methods: when the workloads among PEs become unbalanced, the algorithm prefers to adapt the heavy-loaded flows; the successive packets belonging to the same flow can be remapped to another PE in case of flow timeout. The simulation results show that this algorithm with the well-chosen design parameters can gain preferable effects on packet ordering while preserving load balancing, and has better overall performance on load balancing and packet ordering when compared with other algorithms.(3) Based on the characteristics of the packet buffer memory in NPs, a multi-channel packet buffer memory system with the scheme of Pipelining Input and Parallel Output (PIPO) is proposed. PIPO schedules the write-required sequence with pipelining on the input and processes the read-required sequence in parallel on the output. Both actions in PIPO use memory access policy to improve the effectiveness of memory access. The effectiveness of PIPO, adaptive capacity of variable packet length and extensibility of buffer bandwidth are evaluated by theoretical analysis and simulation experiments with extrapolated workloads. Compared with traditional memory scheduling schemes of packet buffering such as FCFS, PIPO gains better effectiveness of memory access and higher utility ratio of buffer bandwidth, meanwhile incurs less jitters of instantaneous bandwidth on both inputs and outputs.Furthermore, the prototype system of network processor based on SoPC (System on Programmable Chip) is implemented on Altera FPGA. Four soft processor cores (i.e. Altera Nios II) are embedded into the prototype chip which can support four 1000Mbps Ethernet interfaces through co-processor acceleration under software control. Instruction set extension and co-processor sharing schemes for parallel processing architecture of NPs are analyzed and evaluated in depth in the prototype. Meanwhile, the F2CL-based packet scheduling algorithm is verified. The work in this dissertation can serve as an important guideline for the design of NPs.