Packet Processing Engine Parallel Architecture Design And Implementation On Commodity Multi-core Processor

With the decelopment of many new technologies and applications such as Cloud Computing,Internet of Things,Big Data and the unprecedented growth of Intelligent Terminals,requires the network must be able to be customized and programmed like the user applications,specialized hardware network devices has been very difficult to adapt to the needs of quickly deploy,flexibly manage and control,and open collaboration by businesses and users.Software routing devices more stress on programmability and scalability,and more concentrate on application-oriented,diversification,and high-performance tasks processing ability under the premise of ensure forwarding performance,be widely recognized by the industry recently.But compared to specialized hardware network devices,software routing devices is completely behindhand on the packet processing speed,be limitd by the software architecture of operating system protocol stack and processing performance of the CPU.With the rapid development of commodity multi-core processor represented by Intel,the packet parallel processing performance has reached to 10-40 Gbps,and is expected to break through 100 Gbps in next few years,in consideration of next routing devices`s demand at multi-business and high-performance fuse,the routing devices based on common multi-core processor has become a hot research field about network.This paper aim at the architecture of packet processing engine based on commodity multi-core processor and problems about performance optimize,proposed a DMP(Dynamic Multitask Parallel)architecture at the multitasking pipeline thought,using parallel pipeline technology of serial and parallel mixed(serial between tasks clusters,parallel within tasks clusters),decompose the entire processing sequence into more tasks and assigned them to multiple processors be operated,to take full advantage of processor parallelism;then proposed a dynamically self-adaption load balancing task scheduling mechanism based task replication strategy to avoid pipeline bottlenecks caused by inequality among task clusters,and to ensure the load balancing among cores by dynamically self-adaption scheduling mechanism,to avoid throughput decline caused by congestion,increase the utilization of processor resources;and finally,puts forward a lockless ring based communication mechanism,to substantially reduce delay overhead introduced by synchronization and mutual exclusion.compared with traditional ways using synchronization and mutual exclusion,can reduce 80% communication delay,has raised about fourfold in communication performance.