The Research And Experimental Analysis On Testing Method Of Redundant Faults In Digital Circuits

With the development of IC design and produce technology, testing of very large scale integration(VLSI) has become a very difficult problem, the theory and technology of design and design for testability has become an important research direction in VLSI area, there is very high value in theory and practice.At present, voltage testing and IDDQ testing are used at large for digital circuit testing in industrial circle. As a supplement of traditional testing methods, IDDT Testing is proved that it is able to detect some stuck-at faults which can not be detected by traditional testing methods——namely redundant faults. It is helpful for improving the fault coverage of digital circuit testing.Firstly, a test generation algorithm aim at redundant faults which based on IDDT testing is presented. This algorithm uses the difference of delay between different paths in reconvergent fanout structure to engender a risk at the reconvergent node, in order to activate and transmit the fault.Secondly, aim at the redundant faults that are the most difficult to detect in C432 circuit and all of the redundant faults in ISCAS'85 benchmark circuits, SPICE simulation is carried out with the testing vector pairs which are generated by the algorithm. The result shows that the testing vector pairs thich are generated by the algorithm are able to make enough difference between fault-free circuits and fault circuits, achieve the purpose of fault testing, increase the fault coverage effectively.Finally, produce a chip which is used for testing for the sake of deep research in IDDQ testing, try to verify the feasibility of the fault testing method which is presented through the actual IDDT testing, and then guide after work. Though the process is suffered from some external reasons so as to cannot achieve the purpose, these works can guide the next works and make enough preparative for the further research.