Design And Implementation Of High Speed Reusable SPI Bus With Verilog HDL

Compared with parallel buses, the advantage of serial buses is that their structure of circuit is more simple. Recently, increasing with the requirement of the functions and performances of devices, the demand for multiple peripherals microprocessor is enhanced. Thus, serial buses have an extensive application in this aspect.SPI (Serial Peripheral Interface) is a 3 line synchronous full-duplex serial communication interface bus. Many devices such as LCD, FLASH, EEPROM, Input/Output devices, adopt SPI. However, in many other aspects, microcontroller and microprocessor have no SPI interface, the shortcut is to integrate an SPI core to the chip.In this thesis, a high speed reusable SPI bus is designed based on the universal SPI specification. In the design, the variables are supposed to be parameters, which can be altered easily in the project (application), embodies the reusability sufficiently.Due to the lack of responsion mechanism, SPI calls for strict timing order. Thus a special clock-generate model including divider of even and odd integer is designed, which can generate a stable and reliable synchronous serial clock.The spi_shift model, which performs parallel data conversion for serial and reverse direction, has a simple circuit. Although it needs only a few hardware, it is characterized with strong function, for example, the maximum bit of each transfer is variable, up to 128; the transmission speed is faster than other components based on SPI specification.The algorithm of the high speed reusable SPI is implemented with Verilog HDL, adjusted with QuartusП, simulated and verified with ModelSim finally.