Development Of Software Simulator And Research On Fetch Policies Based On SMT For EPIC

It becomes more and more difficult to aggressively exploit ILP (Instruction Level Parallelism). Thus TLP (Thread Level Parallelism) exploiting is becoming a hot researching issue for microarchitecture researchers. SMT (Simultaneous Multitlireading) processors execute instructions from different threads in the same cycle, which has the unique ability to exploit ILP and TLP simultaneously. DSMT (Dynamic SMT) integrates dynamic threads extracting and threads switching mechanism into SMT architecture, which further improves the ability to exploit TLP parallelism. Based on the software-hardware cooperation, EPIC (explicitly Parallel Instruction Computing) can effectively exploit ILP with relatively low hardware complexity. A new microarchitecture called EDSMT was proposed to expand EPIC with simultaneous multithreading execution.This thesis develops a software simulator EDSMTSIM for EDSMT, which adopted the trace-driven simulation methodology. Key components of this simulator, such as pipeline, branch prediction, memory subsystem and dependency control, was carefully designed. The design methodology as well as implementation of EDSMTSIM is described in detail.Instruction fetching is a bottleneck of SMT processors, and fetch policy is well studied for superscalar processors. EPIC is totally different from superscalar in microarchitecture, so in order to develop instruction fetching policies for EDSMT, different factors should be further and especially considered.Instruction fetching policies are carefully designed here, and three new fetching policies are proposed, including SICOUNT, GSave++ and BRCE. SICOUNT takes into account the stop bit and function unit hints in the instruction bundle template when choosing thread for fetching. GSave++ flushes only part of the resources occupied by the blocked thread when a load operation encounters cache miss. The hardware for GSave++ policy is also described in detail. BRCE implements a simple new confidence estimator to reduce the wrong-path instruction fetching. Simulation results show that by using those new policies, higher performance and processor resource utilization rate can be achieved.The research of this thesis will contribute to the future research work of SMT architecture based on EPIC.