Research Improvements Of Performance And Power Consumptions For Simultaneous Multithreading Processor

Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle. In SMT processors, functional units that would be idle due to instruction level parallelism (ILP) limitations of a single thread are dynamically filled with useful instructions from other running threads. By allowing fetching instructions from other threads, an SMT processor can hide both long latency operations and data dependencies in a thread. These advantages increase both processor utilization and instructions throughput.SMT had more than the traditional single-threaded processor power, but the specific power consumption of each thread's contribution to the overall different. This thesis proposed based on thread-level consumption of assessment methods and corresponding fetch scheduling. The strategy can run in the system in the process, the statistics of dynamic parts of the thread on the details of the power situation in each year are generated for each thread to measure the power consumption of sort. Fetch in the next cycle, the processor's power consumption based on the size of each thread dynamically fetch. Thus, in both the system performance based on the operation of the system as much as possible to reduce the peak power consumption, reducing system power consumption during operation is too large for the local lead "stop-go" phenomenon generated. Fetch with the traditional strategy ICOUNT compare experimental results show that:the average weekly decrease of 4.87%peal power, average power consumption per cycle can be reduced by about 2.3%. In th best case, the peak power can be reduced by about 60%, can reduce system powe consumption during operation is too large of a cycle, or a power off time is too large causing the processor a "stop-go" phenomenon probability of occurrence.In addition, this thesis implemented the DIP Cache replacement policy on th SMT, the Cache on the original changes in the structure, the use of a nev replacement algorithm to verify the performance of SMT changes. LRU replacemen algorithm with the traditional comparison results show that:in the single-threadec case, the part of the thread can get some improved performance, in which art can increase the performance nearly 25%, but with the increasing number of load, due to competition for resources level continues to increase, causing the Cache of the algorithm will continue to reduce the failure rate. We also learned from the experimental observation, sampling group, private, and there are.also operating as certain systemic effects of sampling when using a private group, the overall increase in the sampling group, the system performance close to ICOUNT performance. Bu the overall performance did not improve performance under the CMP systerr obvious.