Research And Implementation Of Instruction Fetch And Thread Selection In Multi-threaded Microprocessor

Due to the promotion in technology and application, Multi-threaded architecture has become the mainstream architecture of high-performance microprocessors. Multi-threaded Microprocessors can exploit ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), which has taken full use of the pipeline and the chip area, and throughput is improved accordingly.In this paper, instruction fetch policy and thread selection machanism of Multi-threaded Microprocessors are analyzed deeply, and how to design Cache is detailed. Based on these, the instruction fetch unit and the thread selection unit are designed and implemented according to the feature of the X processor, including ICache, ITLB, CMB (Cache Miss Buffer), instruction buffer, address generation logic and thread selecting logic. Then, the instruction fetch unit and the thread selection unit are verified and synthesized. Based upon module-level, part-level and system-level verifi-cation, the correctness of the design is ensured further. The results of synthesis show that the instruction fetch unit and thread selection unit satisfy the requirement of X processor.This subject is part of the national significant project "High-Performance X Processor". The results of the research and design will be directly applied to this project.