Research On Resource Sharing Control In Simultanecous Multithreading Processors

With the continuing advancements at an exponential rate in VLSI technology, the volume of resources integrated into a processor chip will increase rapidly. How to make efficient utilization of these resources is the key to exert processor's performance. Simultaneous MultiThreading (SMT) processor takes advantage of both thread level parallelism and instruction level parallelism via concurrently executing instructions from different threads. Its fine-grained resource sharing and long latency hiding brings good performance improvement. However, threads compete for common resources rather than they share them in SMT environment, unreasonable resource competing will result in resource clogging, abusement and wastage. The rationality of resource sharing control determines the throughput performance for processor and the fairness between threads. With the ever increasing performance gap between processor and memory, the long latency from off-chip memory access will make the resource clogging and abusement in SMT processor more eminent. Moreover, threads change their requirment of resources with the the change of their program behavior when they compete for resources, it is difficult for an unadaptable resource sharing control policy to supply continuing optimization of resource distribution. All these problems especially augment the signification of how to reasonably control the sharing of SMT processor resources among the threads.According to the problems mentioned above, this dissertation, after a deep study on related works, launched the research in four approaches: preventing long-latency-load dependents from clogging common resources, exploiting the concurrency of compute and memory access operations for hiding of off-chip memory access latency, making the resource sharing control policy adaptable to changing program behavior, and eliminating the influence brought to the critical pipeline by those cycles spent on making resource control decision. Corresponding resource sharing control policy for SMT processors was present per approach, and their validity were proved through simulations. The main contributions are as follows. (1)To prevent instructions dependent on long-latency loads from clogging the common resources, a long-latency-load awared dispatch policy for SMT processors is proposed. This policy decides on whether a thread should be dispatch-stalled at the dispatch stage in the pipeline according to the detected or predicted L2 cache miss information. By preventing those long-latency-load dependents that have been fetched from clogging the common resources after detection of long-latency load, and reducing the feedback latency of the L2 cache miss information, it alleviates the negative influence brought to the resource sharing in SMT processor by long-latency loads.(2)To address the problem of hiding long latency of off-chip access, a resource partitioning policy for SMT processors exploiting the compute-memory concurrency is proposed. It follows the essential feature of SMT processors that hide long latency by exploiting thread level parallelism, tunes the resource partitions among the threads periodically according to the concurrency level of compute-memory operations of each thread, and provides more resources to the thread that has better performance in compute-memory concurrency. This policy improves the proportion of time for concurrent compute-memory executing to the whole executing time, providing effective hiding of long latency brought by cache-miss loads.(3)To avoid the stagnation in the suboptimal resource distribution spaces in the resource distribution optimization procedure, and enhance the capability of performing a continue optimization for resource distribution for changing program behavior, a spatially triggered dissipative resource distribution policy for SMT processors is proposed. In this policy, the self-organization mechanism cooperates with the spatially triggered chaos for the distribution solutions. By taking control of the similarity of the distribution solutions, the policy can escape from the suboptimal solution, and supply persistent optimization for resource distribution in different program phases. The throughput and fairness performance are both improved by taking only the throughput as the optimization target.(4) A design model of non-critical path resource distributor for SMT processors is proposed, which separates the resource distribution module from the critical pipeline path to avoid the clock wastage caused by the computation on the allocation solutions. The asynchronous work mode of this non-critical path resource distributor is also meaningful for those implicit resource sharing control policies that consume obvious cycles in making decision.