Study On Fault Diagnosis And Design For Testability Of Analog And Digital Mixed System Based On Boundary Scan

The rapid development of microelectronics and semiconductor technology,as well as the chip wafer particle miniaturization, makes the scale of integratedcircuit increase and become more and more complex, meanwhile the structure ofthe board also has become increasingly complicated. Electronic equipments alsopenetrate to various industries owing to the fuzz boundaries between industries.Therefore, the reliability of electronic devices become more and more focusedon, and people compress higher requirements on the testability of the electronicequipment. The traditional test methods for electronic equipment cannot meet theexpansion of the circuit scale, and the circuit testability and convenient methodsof testing and designing skills urgently need improving. Boundary scan, thetechnology of design for testability (DFT), emerged in these voices. Boundaryscan technology, proposed by JTAG and IEEE organizations, uses virtual probeinstead of the traditional physical probe. In this situation, only4test lines will beable to complete the testing of inner core function of the chip components,connection between chip and PCB board, and chip-to-chip interconnection. Sothe circuit testability is greatly improved.During the thesis process, the following work is mainly done:Firstly, deeply analyze the theory of analog and digital circuit faultdiagnosis, including their respective characteristics when using these methods intest. Then propose a relatively quick and ease test method, which can provide atheoretical basis when reserve measurable nodes during designing a testablecircuit.Secondly, deeply analyze two boundary scan standards, which areIEEE1149.1std for digital signal testing and IEEE1149.4std for mixed signal test, so clear the program to test the circuit containing devices that supportboundary scan standard. On this basis, propose three application programs usingmixed-signal chip STA400, which supports the IEEE1149.4standard, to improvethe circuit testability.As to the circuit realization of the testing of the hardware circuit containingdevice supporting the boundary scan technology, design the test circuit based onFPGA for hardware implementation platform that uses the feature of Cyclone IIEP2C8Q208C8supporting NiosII embedded soft core processor. Realize it underQuartusII and IDE using HDL and C.Combined with the virtual instrument technology, use HDL and example aRS232interface on the hardware for communication with LabVIEW, then realizethe graphical display of test results in LabVIEW environment.In the end, we explained the specific applications of boundary scantechnology to improve circuit testability through an instance. The actualexperimental results demonstrate that using devices supporting boundary scanstandard in circuit can greatly improve the testability of the circuit, and can avoidthe inconvenience of increasing mechanical switch in traditional test. The FPGA-based programmable design characteristics also make the actual meaning.