Dvb-c Digital Qam Receiver Timing Synchronization Module Design And Verilog Implementation

The design and verilog realization of the timing recovery in the QAM demodulation of all-digitized DVB-C receiver has been completed in this project. The demodulation system includes timing recovery, frequency recovery and equalization. The subsystem of timing recovery consist of interpolator, timing error detector, loop filter and NCO controller. It realizes the signal synchronization by getting timing error and feedbacks them to control the interpolator. In the paper, the principal of DVB-C theory is introduced firstly, then, the software and platform used in the project are mentioned simply. The theory of timing recovery is recommended detailed in the fourth chapter. In the fifth chapter, the arithmetic design in matlab as well as the simulation and the analysis are discussed. Afterwards, the verilog realization of timing recovery is completed. What penman have done in the project are listed below:Read papers associated with my project and get familiar with basic principal of the system.Make clear the frame of the system with teammates and make the interface criterion.Complete the design of timing recovery in matlab, carry the simulation and analyze the result.Realize the timing recovery in quartus.