A Scheduling Scheme Of CICQ Switch Fabrics With Buffer Logical Sharing

Along with the explosive traffic expansion in the Internet and together with the rapid bandwidth growth of optical networks, routers, as nodes in networks, are gradually becoming one of the most urgent bottlenecks in the process of developing networks. Moreover, the switching system is the key factor which limits the performance and capacity of routers.With the goal of implementing the switching module in the terabit router, this paper gives a thorough analyses and comparison of the state-of-the-art of queuing disciplines and scheduling algorithms, as well as a briefly explanation of some feasible solutions at present. At the same time, a detailed analysis is made into the performance requirements of the switching module, in view of the demands of "The basic platform and experiment system for terabit scalable high performance IPv4/IPv6 routers" project, which is supported by the National High-Tech Research and Development Program of China (863 Program) under grant number 2004AA103130.And then, a novel scheme of Exceed Threshold First Round Robin, referred as ETFRR in this paper, is proposed to solve the problem which is caused by the limit to the capacity of the corsspoint buffer in a single chip under today's ASIC technology. The ETFRR algorithm can be used at the stage of the output queue of the CICQ, achieving logically share of crosspoint buffers, reducing packet loss ratio under the scenario of non-uniform traffic, and providing delay guarantees. The simulation shows that the packet loss ratio of RR-ETFRR is lower than RR-RR.Finally, the hardware implementation of CICQ and RR-ETFRR is presented, which provides a practical reference for the implementation of the switching module in the terabit router. The test results show that the terabit router based on our scheme of switching module can completelysatisfy the requirements of Technical Specification for High End Router.