Terabit Routers Exchange Network

Along with the explosive expansion of the traffic carried by the Internet and rapid bandwidth growth of the optical transmission network, routers, which act as network node, have inevitably become bottleneck in the development of networks. However, the switching system is the key factor which limits the performance and capacity of routers.Aiming at the switching network implementation of the terabit touter, this dissertation analyzes and compares the queuing structures and scheduling algorithms in existence, concludes the factors that affect the implementation and scalability of high-performance switching systems. And according to the requirements on one of key projects of the National High-Tech Research and Development Program of China (863 Program) for the Tenth-Five-year Plan" The basic platform and experiment system for terabit scalable high performance IPv4/IPv6 routers", this dissertation also analyzes the demands of the Terabit Router's switching network, and provides a combined input and output queued with buffered crossbar (BC-CIOQ) architecture which can support the variable-length packets, furthermore, provides a modified parallel packet round-roubin (MPPRR) algorithm which not only can schedule the variable-length packets, but also can be facile. Finally, this dissertation shows the material implement for BC-CIOQ architecture and MPPRR scheduling algorithm. By these implement scheme, we provide a switching-network which can scale up to the terabit for the project. The test result shows that it can completely suffice the performance requirements of the switching-network for the Terabit Router Project.The key contributions of this dissertation include: A novel architecture supporting variable-length packets, named as combined input and output queued with buffered crossbar (BC-CIOQ), is presented, based on the requirements of variable-length packets traffic. A modified parallel packet round-roubin (MPPRR) algorithm for BC-CIOQ architecture supporting variable-length packets is presented to reduce the delay and size of the crosspoint buffers, due to the scheme of store-and-forward in traditional packets scheduling algorithm. By using BC-CIOQ architecture supporting varibale-length packets and MPPRR algorithm, the switching module whose throughput can achieve 160Gbps is turned into reality, which has already been used to build the terabit switching-network for the Terabit Router Project.