Research On Key Technologies And Implementation Of The Switch Based On CICQ Structure

With the continuous growth of network applications and traffic,the demand for efficient high-performance switching equipment is increasing.To achieve this target,switching equipments are achieved based on the virtual output queuing(VOQ)structure.With the VOQs setting at the input ports,the memory bandwidth could meet the increasing demand,and the HOL blocking problem will be relieved.However,VOQ structure requires centralized scheduling algorithms to perform scheduling,and increasing the number of the port and data rate limits the scalability of centralized scheduling algorithms.On the other hand,CICQ structure has advantages over the traditional VOQ switch,and has the potential to solve the complexity and scalability issues of VOQ structure.Internal crosspoint buffers separate the input and output ports logically,to achieve a simple distributed scheduling,meanwhile greatly easing the input and output conflicts of the VOQ structure,and has better switching performance.High performance CICQ switch requires good scheduling algorithm for arbitration,which need several basic characteristics: high throughput,low latency,service fairness,fast scheduling and easy hardware implementation.Taking CICQ switch fabric as the main research object,this dissertation mainly focus on improve the delay performance and fairness of key algorithms,and complete the design and implementation of a 4 × 4 Fibre Channel(FC)switch based on CICQ strcuture.In order to verify the functionality and performance of the switch,a traffic generation solution which could accurately simulate the generation of real network traffic flows is proposed.A hardware/software co-verification platform is designed and established to complete the performance test of the Fibre Channel switch.The main work and innovations of this dissertation are as follows:(1)Aiming at the problem of unable to meet the delay performance and fairness for existing scheduling algorithms,two high-performance CICQ scheduling algorithms named MCQF_RR(The Most Critical Queue First-Round Robin)and IMCQF_RR(Improved Most Critical Queue First-Round Robin)are presented.Performance simulation results show that the proposed algorithms are able to maintain good delay performance and stability comparable to existing LQF_RR algorithm under uniform and non-uniform traffic.In addition,service fairness of several major algorithms is analyzed.The novel algorithms using the most critical queue first service policy at the input scheduling,improve the fairness performance significantly compared with LQF_RR.(2)As for the packet segmentation scheme in the variable-length packet switching,an efficient adaptive packet segmentation scheme named Adaptive Multipacket segments(AMS)is proposed to solve the inflexibility and low switching efficiency of existing segmentation mechanisms.Experimental results show that the CICQ structure with AMS scheme exhibits good delay performance under different traffic models,and significantly better than the existing best performing Variable-size Multipacket segments(VMS).(3)Based on the study of CICQ structure and new scheduling algorithm,a CICQ switch architecture based on the Fibre Channel(FC)protocol is designed,to realize the function of FC-0,FC-1,FC-2P layer protocol and packet switching.For variable-length frame switching,since the Fixed-size Unipacket segments(FUS)has the advantage of simple implementation,it is chosed to accomplish the segmentation of variable-length frames in the frame segmentation module.For existing implementation technologies of FUS have the disaavantage of high delay and complicate storage management,a new pre-segmentation method is proposed and used in the frame segmentation module,to achieve low segmentation latency and simple data management,and further benefit the improvement of the overall switching performance.(4)Regarding the traffic generation scheme of switching equipments,traffic patterns commonly used to assess the performance of network equipments are analyzed.Appropriate traffic patterns are chosed as the test vector in the performance testing of Fibre Channel switch.Based on existing traffic generator solutions,an aggregation process-based traffic generation model is proposed,and the architecture of novel efficient traffic generator is designed according to this model.With the configuration flexibility of the processor and the high-performance of FPGA hardware,the proposed traffic generator is capable of generating real-time traffic of Poisson process and self-similar process.The generated traffic can achieve high data rates and good scalability.Statistical analysis results show that the traffic time series produced by the aggregation process-based traffic generatator can simulate ideal traffic models accurately.(5)A hardware/software co-verification platform is designed and established to complete the performance testing of the Fibre Channel switch,and the software and the hardware of the platform are described separately in the paper.The effective traffic generator proposed is applied to the verification and testing of the switch,to generate traffic approximate the behavior characteristics of real traffic.Performance verification of the FC switch is achieved based on the hardware/software co-verification platform,and analysis of the actual test results are completed.