The Research And FPGA Implementation Of CICQ Switching Fabricin Router

With the expanding of the application on the Internet, the area of the business on the Internet has been changed from the simple data business to the multiple business such as voice service, video service, game business and so on. Networkinterconnection devices such as routers and switcheshave been become the critical devices for the performance of the Internet, in which switch fabricsarethe key units in routers and switches and determine the performance of the routing equipment. So far, the switch fabric and the scheduling algorithmhavebeen becomethe hot research topics.In thisthesis, weanalysesthe shortage of switch fabricsused currently. We designs a CICQ switch fabric based on APRR scheduling algorithm, anda user-defined register bususedin the router. Wehave implemented a CICQ switch fabric and a user-defined register bus onthe FPGA platform ofthe Xilinx company.In the input port, weuse Virtual Output Queue to eliminateHOL blocking efficiently, which the packet drop rate hasbeen reduced. We design a programmable priority encoderusedthe thermometer encode and the contrary thermometer encode. weuse the APRR scheduling algorithm to improve the exchange capacityof the switch fabric, anduse two-level pipeline to reduce the time delay of the message.Then we have implementeda 8*8 CICQ switch fabric on the Virtex-5 chip. The simulation has been done. It shows that the message transmissiononly spends8 us from the input ports to the output ports. The FPGA synthesis of the CICQ switch fabric designed in this thesis shows that 26008 slice registersoccupiedabout 31% of the chip resources has been used,18632 LUTsoccupiedabout 22% of the chip resources has been used, and 96 Blocks of RAM occupied about 32% of the chip resources has been used.In thisthesis,a register bus has beendesignedbased on the user-defined register bus protocol, which includes only one bit control line and one bit serial data line. We improve the security of the data transmission withverifiedthe frame header and the frame footer. Thenwe implement the register bus on the Virtex-5 chip. The simulation has been done. It shows thatthe CPU is able to read or write the router table correctly.The FPGA synthesis of the register bus designed in this thesis shows that register resourcesoccupiedless than 1% of the resourceson the chip have been used.We design the router used the CICQ switch fabric and the user-defined bus, then test the performance and the functionof the routerby using the IXIA network analyzers.wetestExchange Capacity,Link Rate, Forward Delay Timerand Loss Rate. The results of the tests show that Exchange Capacity is higher than 10 Gbps,LinkRate is higher than 1.5Gbps, Forward Delay Timer is less than 25 us, and Loss Rate is less than 10-6. The router designed in this thesis can match the application requirements.