Research And Implement Of Access Convergence Router's Switching Network

The coming information age brings the explosion of the Internet information growth. And this requires new networking devices to transfer, exchange and process the huge amount of datum in real time. The rate of the transmission has been greatly improved due to the widely use of optical fiber these yeas. But the rate of switch is becoming the bottle neck of the whole internet growth because of the relatively laggard progress of the switch theory and technology. So the router with huge capability and high performance becomes the key of the network technology development.Given the 863 project requirements for "the research of performance and key technology of access converge router (ACR)", this dissertation is devoted to the researches of high speed scheduling algorithm from switching architecture model viewpoint in both theory and implementation. Based on the analysis and comparison of scheduling algorithms in existence, we propose a combined input and switch fabric queuing (CISFQ) architecture, and prove that the architecture can give 100% throughput and rate guarantee. According to the CISFQ architecture a variable-length packet scheduling algorithm is described for efficiently accommodating IP traffic. And we give the implementations in ACR.The works of this dissertation contains:1. Researching the principles of buffer configuration within different architectures; analyzing and comparing the advantages and disadvantages among various switch fabric; pointing out the challenges of implementing high speed exchange, QoS assurance and multicast supporting. Supplying references for the design of ACR's switching network.2. Proposing an architecture of "Combined Input and Switch Fabric Queue (CISFQ)" according to the practical requirement of ACR. This CISFQ architecture can eliminate the collisions among the different input ports by adding matching buffers. Demonstrating the CISFQ architecture from the performance viewpoint, especially when the arrival process obeys a strong law of large numbers, the architecture gives 100% throughput and rate guarantee. These works establish the theory basis for the design of ACR.3. Improving the existing RR/RR scheduling algorithm and proposing a more realizable scheduling algorithm called packet-based RR/RR, given the situation of variable-length packets transmitted in the network; elementary analyzing of how to implement multicast in switching network..4. Implementing 160Gbps switch unit on FPGA within the framework of ACR according to the proposed design architecture. By adding input-switch modules and output-switch modules, we expand the capability up to Terabit.