FPGA Implementation Of Infomax BSS Algorithm

Blind source separation (BSS) has been an active branch in signal processing field since 1990s. The specific advantage of BSS is that it can recover a set of unknown mutually independent source signals from their observed mixtures without knowing the source signals and the mixing coefficients. Therefore, it has been widely used in the telcommunication, biomedical engineering, speech and image processing, etc.Information maximization (Infomax) algorithm is a distinguished BSS algorithm proposed by Bell and Sejnowski based on the information theory .The Infomax yields excellent results for separating supergaussian signal sources such as speech signal. Thus it is much more suitable for speech processing with high quality in telecommunication, multimedia, speech identifiers. However, its convergence speed is slow due to the computation complexities. In a word, the Infomax algorithm can not separate the signals in real-time.To present a real-time solution to Infomax, this thesis proposes its hardware implementations based on FPGA. The main works are as follows. (1) By deeply analyzing the principle and function the algorithm, it is divided into five modules including the input module, the matrix multiplication module, the judgment module, the weight adjustment module and the output module. (2) Each module is designed based on the FPGA. The design of the weight adjustment module is emphasized since it is the core of the hardware implementation. LUT method based on ROM is used to implement the nonlinear function in the algorithm. (3) The matrix multiplication is developed by serial structure, parallel structure and series-parallel structure, the serial structure is eventually used by comparing the performances of three kinds of structures in MAX+PLUS II. (4) By using the custom fixed-point number representation, the design and simulation of each module and the algorithm are completed, and the simulation results are analyzed. (5) Based on the 18-bit floating number representation, the improved multiplier, division, adder and comparator is given, and then the floating arithmetic is completed.