The Research And Design Of UTOPIA Interface Component On High Performance Fixed-point DSP (XDSP)

As a cell-based Asynchronous Transfer Protocol, ATM has the advantage of high-speed information transmission, multiple service integration, and dynamic allocation of bandwidth and connection management. The UTOPIA, which was defined by ATM Forum as an important equipment-internal interface, is the physical realization of the logical boundary between physical layer and ATM layer. Combined with ATM technology, the ability of processing high speed digital signal contributes to extensive application of DSP in communications. Based on the demand of the independent high performance fixed-point DSP-XDSP's system framework, a kind of UTOPIA interface component which will make this DSP be used in ATM communications networks is designed and implemented.After analyzing the UTOPIA protocol, the UTOPIA's framework is designed. According to its internal data flow path, the UTOPIA is divided into four parts, slave transmit queue, slave receive queue, DSP access module and clock detection module. The first two parts interface to an ATM master controller whose inner structure and the state machine generating the interface timing are designed in detail in order to meet the function of cache cell. DSP access module interfaces the EDMA and the CPU in the DSP. Taking the various abnormal situations of the EDMA with CPU and UTOPIA occurring in communication process into comprehensive consideration, a complete exception handing mechanism is set up in this paper.Basing on the feature of the UTOPIA that transports data in cell, asynchronous wide register is designed as the cell buffer. Compared with the traditional asynchronous FIFO, asynchronous wide register is easier to operate and more reliable, thus the security problems in data transfer across clock domains between the ATM level device and the DSP internal module can be settled.Modular verification has been accomplished based on the research of the contemporary main verification strategy and method on the microprocessor. After researching the transaction-based verification methodology, the IP core of the ATM level master device is designed in connection with the UTOPIA in the XDSP to verify and test whether the interface timing is satisfied with the protocol requirement. The system-level verification model based on FPGA is designed as the platform to design the transaction-based verification method and process verifying UTOPIA interface.