Research On HIMAC3.0 Queue Management And Cache Management Technology

With the promulgation of the "14th Five-Year Plan",China plans to vigorously promote the construction of new infrastructure,develop the digital economy and apply 5G technology.The above scenarios all put forward new requirements for network infrastructure,especially the access network which is directly related to user experience.As China's independent and controllable fiber coaxial hybrid access technology,HINOC has experienced the first two generations of standard formulation and chip commercialization,and has developed to the third generation.The third-generation HINOC technology will support line-speed processing of 10 Gigabit Ethernet,support up to 128 users to access,and support multiple HIPHY channel binding of the device.Combined with the laboratory scientific research project "Research on the Core Communication Mechanism of HINOC Ten Gigabit Coaxial Broadband Access",this thesis focuses on the queue management and buffer management technologies of HINOC MAC layer.This thesis first briefly describes the background and application scenarios of HINOC technology,compares the similarities and differences of the previous two generations of HINOC technology,and then proposes the technical indicators of the third generation of HINOC technology as well as the design requirements of queue management and buffer management.Second,it lays a foundation for the design of HIMAC queue management and buffer management by studying the two-level buffer chain management scheme and the onchip and off-chip joint buffering scheme.By studying the buffer overloading mechanism of the priority queue,an active priority Qo S is provided for HIMAC3.0 network.Third,the overall framework of HIMAC is designed according to the design requirements of HINOC3.0,and the various sub-modules of HIMAC3.0 are briefly introduced and structured.Fourth,this thesis focuses on queue management and buffer management module.Submodules such as enqueue control,Ethernet frame backpressure rebound control,dequeue control,queue information management,buffer management,enqueue bus control,off-chip bus control,sending bus control,internal cache interface,external cache interface are carried on the detailed design and inteface specifications.Fifth,by constructing a self-loopback simulation environment on the HIMAC PHY side,the functional correctness of the HIMAC queue buffer management as a whole and each sub-module is verified.Finally,based on Xilinx's XCVU13 P chip and Spirent's network test platform,the HINOC MAC layer is tested on the board which verifues the functional correctness of the HIMAC design.The innovation of this thesis has three aspects.First,a two-level buffer management scheme is designed to allow queue management module to manage larger cache space while consuming less overhead.Second,the on-chip and off-chip joint buffering scheme is designed,and the model of DDR pre-read data is constructed.The pre-read data frames are stored in the on-chip FIFO buffer for subsequent dequeue movement,which improves the bandwidth utilization rate of DDR and reduces the data forwarding delay to a certain extent.Third,this thesis designs the overload mechanism that high and medium priority queue can occupy the buffer area of the middle and low priority queue,which avoids the problem that the high priority queue cannot get the shared cache area in time under the passive backpressure and rebound mechanism of HINOC2.0 priority queue.