Design And Implementation Of High-speed Large-capacity Queue And Buffer Management Based On DDR

In recent years,the demand for high-speed broadband network transmission has brought new demands and challenges to real-time networks,and it has become a hot issue for industrial research in various countries.Ethernet technology is the most pervasive network communication protocol available today for LAN applications and its technology is quite mature.However,in areas where high real-time performance and reliability are required,such as aerospace,rail transportation,and high-end industrial control,the best effort mode of traditional Ethernet obviously cannot meet the demand.Based on this background,time-triggered Ethernet has receiver extensive research and application.Time-triggered Ethernet combines the real-time,deterministic,fault-tolerant capabilities of time-triggered transmission with the flexibility and dynamism of traditional “Ethernet best effort delivery” to meet the communication needs of various types of traffic,and is an important new type of comprehensive network transmission technology suitable for future industrial control.In this thesis,combined with the project undertaken by the laboratory,“High-bandwidth Time-triggered Ethernet Switch”,based on the problem that on-chip resources of FPGA are limited and cannot meet the memory capacity requirement of TTE switch,a design scheme for a DDR-based queue management unit is proposed.Firstly,the research background and basic concepts of time-triggered Ethernet are introduced.Secondly,the general architecture of the TTE switch is introduced.According to the different characteristics of the two major types of services,a design scheme is proposed in which the TTE switch is divided into two planes to process time-triggered services and event-triggered services and the processing flow of various services is briefly described.Thirdly,the queue buffer allocation method and buffer address management method are proposed,and the key modules of the management channel of the DDR-based queue management unit are designed and implemented,including the enqueue scheduling module,dequeue scheduling module,queue information management module,and buffer management module.Fourthly,the receiving bus control module and sending bus control module of the data channel of the DDR-based queue management unit are designed and implemented.Finally,the key modules of the queue management unit are simulated and analyzed,and the board-level test results and problems are analyzed and explained,thereby verifying the validity of the design.The innovative points of this thesis include,firstly,the use of off-chip low-cost,large-capacity DDR and SRAM combined cache architecture,where DDR as the main body of cache data,provides large-capacity data storage,SRAM is used to store buffer description and queue information;Secondly,the queue management unit are divided into management channel and data channel,to process data frame status information and payload data in parallel to meet the line-speed processing requirements of the queue management unit;Thirdly,the method of storing information in the FIFO of the first word fall through mode and the parallel processing method of enqueue and dequeue compress the operation cycle of enqueue and dequeue of data frames,thereby improving the processing speed of enqueue and dequeue of data frames.