Design Of Hardware And Implementation By ASIC For Intra Prediction Decoder Based On H.264 And AVS

The application of multimedia video compression technique grows very rapidly with the development of information technology and digital signal processing&transmission. . Then the new video compression standard H.264 and AVS comes out. Compared with the MPEG-X and H.26X compressed video standards that were establish before, the H.264 standard can offer much better video pictures and compressing rate. So its foreground is very wide. A lot of company and research institute begin to study and make use of such new standard. Because the decoding complexity of H.264 and AVS is very high, software implementation can't decode in real time. The decoder must be implemented in hardware and software.In this paper, a hardware Intra prediction based on H.264 and AVS has been designed Based on analyzing each kind of intra prediction algorithms , this paper proposed a reconfigurable parallel intra predictor according to the similarity of the predicting operations. This unit can achieve system optimization. In order to get realtime decoding performance, eight parallel processors are adopted in the proposed architecture. At the same time, pipeline structure is used in decoding intra prediction mode. Such methods can increase decoding speed.Top-down design method is used in whole design. In order to verify decoding algorithms and provide test vector, c model is designed first. Simulation is made in every design step. At last, FPGA verification and ASIC synthesis are made. The decoder can decode standard-definition video coding in real time and can decode high-definition video coding in real time if implemented in 0 .18μm CMOS.