Design And Realization Of SATA Build In Self Test

Serial ATA is a kind of ATA that is totally different from parellel ATA and it is well known for its serial data transmission. Build-In Self-Test technology realizes the test of the integrated circuit by integrating few logic circuits in the chip and is recognized as one of the effective method to solve the complicated,long cycle and costly test equipment development problem. This article is based on the project"Research and Design of SMIC 0.13μm CMOS process high speed Serial ATA"of SATA Group, Design Service Division, SMIC. It gives us an introduction of SATA physical layer generic architecture and the traditional build-in self-test technology, and brings forward the SATA BIST methodology. Because this method doesn't use memory to store the test patterns, it can save certain area of the chip.Firstly, all kinds of SATA BIST test patterns and their principles are introduced in detail in this article; and then, it brings forward the architecture of the BER test system, and introduces the principle of the BER test system in detail; At last, it introduces the realization and design of the BER test system(including the Verilog code writing,function verification,circuit synthesis,timing analysis,place and routine). And the circuit of this BER test system has been taped out with SMIC 0.13μm CMOS process.