Low Power IC Design Of Systolic Array For Motion Estimation

Motion estimation module is the core component of the video coder, systolic array is becoming the first choice as the computation module in motion estimation because of its regular architecture and easy realization. Its characteristic directly decides the image quality of the video as well as the process speed and power consumption of the whole chip. This thesis aims at proposing low power strategies according to analyzing the power consumption of systolic array. Based on the strategies, low power systolic array structure for motion estimation was designed. It's an important part of the sub-project of lab's research—the pivotal technology of the video coding on SoC, which belongs to System-on-Chip Research Center at Harbin Insitute of Technology Shenzhen Graduate School. Totally speaking, the thesis includes the following parts:(1) Analyzing the data relations in the search area, the FBMA computation model was established to realize the mapping from the algorithm to the systolic array. The array can process data in pipeline in the horizontal direction while parallelly process data in the vertical direction, it is a 8×8 regular structure;(2) Low power strategies were proposed. The first one is through inserting suspended register chains to suspend the useless PE operation. The second one is selecting the sythesizable style Verilog language, which needs less computation and has a high utilization;(3) Combining the low power strategies, low power systolic array for motion estimation was designed. The architecture has 3 kinds of PE, with the suspended register chains inserted at the left and the bottom of the array, it uses the gated clock to suspend the invalid PE operation. The array was described in RTL with Verilog HDL, the Verilog-XL simulator was used to verify the function. With the Synopsys Design Compiler, the module was synthesized, the system clock can run at 100MHz;(4) Two other typical arrays were designed. Both of them adopt delay...