Design And Implementation Of RSA Public-Key Cryptographic Coprocessor Based On Systolic Array Architecture

Cryptography is considered as the main technique to satisfy the requirement of the information security, and a notable character of the modern cryptography system is the combination of the computer technology.Public-key cryptography can efficiently solve the problems such as key distributing and Non-repudiation obtaining, RSA is the few of numerous public-key cryptography that can be used to realize digital signature and ID identification as well as data encryption.The implementation of cryptography based on FPGA integrates flexibility of the software and high speed of ASIC successfully, and it is becoming to be a new trend. This thesis studies on the FPGA implementation of RSA public-key cryptographic coprocessor based on systolic array architecture, the typical Montgomery's algorithm is presented first, in order to make it suitable for implementation on Altera's FPGA, a modified radix-2 version is proposed and then a high-performance architecture is designed for modular multiplication. By adopting pipeline technique, two operations can execute simultaneously, it is adopted to implement modular exponentiation based on modified R-L algorithm. Remarkably, the conception of alterable character is applied in this design, which extends the flexibility effectively.The prototype of the design is fabricated in Altera Cyclone EP1C20F324C8 FPGA, at the utmost clock frequency of 197.78 MHz, the speed of 512/1024bit encryption or decryption rate is about369.0Kbit/s and 93.3Kbit/s. 8915 LEs and 8501 RAMbits are used. The proposed RSA coprocessor based on systolic linear array architecture has distinctive features that not only computation speed is significantly fast but also hardware overhead is drastically decreased.