A Novel Systolic Array Aricthecture For Full-search Block Matching Motion Estimation

Multimedia communication has been most popular in the life. With the development of internet, Multimedia communication has been the most important part. With the improvement of technology, there is an ongoing global trend to shift multimedia applications from traditional platforms, such as PC and smart phone. There is a challenge of video codec for real-time and low-power. The characteristic of Motion Estimation (ME) directly decides the image quality of the video as well as the process speed and power consumption of the whole chip.This thesis aims at proposing low power strategies according to analyzing the power consumption of systolic array. Based on the strategies, Low power systolic array structure for motion estimation was designed. The thesis includes the following parts:(1) Analyze the motion estimation arithmetic and fast search arithmetic, such as 1-D systolic array, 2-D systolic array and tree architecture for the hardware resources,processing rate,I/O ports.(2) Low power strategies were proposed. The first one is through inserting suspended register chains to suspend the useless PE operation.The structure proposed is modeled in virology synthesized using SMIC 0.18um lib, floor planned and verified using reference model. HDTV level video(1920×1280@30fps) could be real-time handled correctly by the array designed with this structure.