| Recent years,with the development of science and technology,the needs of people’s live and social development have led to the emergence of a large number of new applications,which require wireless communication technologies that are more stable,have higher throughput and lower latency.Therefore,the multi-antenna MIMO technology supporting ultra-large capacity developed with the commercialization of the fifthgeneration communication 5G has further become a new research hotspot.While the MIMO system brings large-capacity transmission,the difficulty of signal detection and the hardware design requirements are further increased.Therefore,considering in terms of the improvement of the traditional algorithm and the design of the VLSI architecture using the systolic array,this thesis deeply studies the receiving and detection technology of the MIMO system.Firstly,this thesis introduces the background of the research status and significance of the research,and also introduces the status of the research.Then,the basic principle of MIMO,some traditional signal detection algorithms and the systolic array structure in hardware design are researched and introduced.Because considering whether it is nonlinear or linear signal detection algorithm and its architecture design,there exist problems such as high algorithm complexity,high hardware consumption and low throughput rate.The third and fourth chapter optimize commonly used linear and nonlinear signal detection algorithm,meanwhile design the hardware based on the optimization algorithms.Then the linear signal detection algorithm MMSE algorithm is introduced and six different optimization MMSE algorithm are introduced.Considering the need of hardware implementation,the Jacobi iterative MMSE signal with high parallelism is analyzed from the aspects of computational complexity and convergence speed.The detection algorithm is optimized,and the optimization include:（1）the selection of the optimized initial value;（2）the linear equation is solved by adding the weights,and it is verified that the optimized signal detection algorithm reduces the computational complexity from the theoretical analysis and the simulation analysis.And the convergence speed is accelerated,and can achieve a greater degree of parallelism in hardware designing.Then the hardware implementation based on the proposed optimized Jacobi MMSE detection algorithm is designed.The architecture design is based on the systolic array.The hardware structure of each key module is given and the comprehensive simulation verification is carried out.Considering that the performance of nonlinear signal detection algorithm is better than that of linear detection algorithm,this thesis also researches and optimizes the K-Best detection algorithm.Firstly,this thesis introduces the K-Best signal detection algorithm,and the K-Best algorithm is optimized from the perspective of path expansion,and the performance simulation verification results are given.The simulation results show that the convergence speed is accelerated while detection performance can be ensured.Then,the hardware architecture of K-Best signal detection is proposed,and the optimization includes:（1）designing a QR decomposition detection preprocessing module based on triangular systolic array to speed up the matrix inversion and improve the throughput of the module;（2）designing a new accumulation unit based on vertical accumulator to reduce the accumulations and the complexity;（3）designing a new sorting unit,which combines bitonic sorting and parity sorting to increase the reusability of each sub-module.（4）designing a parallel sorting unit; Compared with other similar designs,the detector based on bitonic and parity sorting units can achieve a throughput rate of while improving the detection performance and the reusability; the detector based on parallel sorting units also has great advantages in terms of detection delay and energy efficiency,which can achieve the minimum latency of 130 cycles and 247 p J/b with throughput of 1220 Mbps. |
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