Research On MPEG4 Coprocessor Based On FPGA

Network bit rate continues to increase (partially in the local area), high bit rate connections to home are commonplace and the storage capacity of hard disks, flash memories and optical media is greater than ever before. With the price per transmitted or stored bit continually falling, why are we continuing researches in image or video compression? Algorithms are becoming more and more complex and the advance is becoming marginal. What is still missing today and what are the applications asking for higher compression rates? From the author's point of view there is one very important application field justifying this effort, i.e. the mobile video service. Spectrum over the air is scarce resource which cannot be enlarged. Even with the advent of UMTS/IMT 2000, the available data rate will be restricted to 144kbit/s for mobile reception; higher rates up to 2Mbit/s will only be available in micro cells, i.e., in restricted areas like offices. 144kbit/s is still a rather limited data rate for video transmission, if available coding schemes like MPEG-4 or H.263+ are used. Therefore it is foreseeable, that radio bandwidth will remain a permanent bottleneck, which justifies all effort for video compression. On the other hand, implementation of these techniques poses several new challenges, especially for real-time applications. To reduce the computational complexity and the power consumption of motion estimation, several fast block-matching algorithms, such as 2-D logarithmic search, three-step search, and conjugate direction search, have been proposed. Although these approaches reduce power consumption, they result in suboptimal solutions, because the search spaces are necessarily reduced. Lowering the supply voltage in motion estimator to save power at the circuit level has been proposed, which results from search window management and demand clocking. However, none of the above addresses the issue of lowering power consumption of the block-matching algorithm at the architectural level without sacrificing the optimality of the solution. This paper presents an architectural enhancement to reduce the power consumption of the full-search block-matching (FSBM) motion estimation and realize the real-time coding. The approach is based on systolic architecture and lower power consumption control circuit. Motion estimation is a compute bound problem that can be efficiently handled by elementary systolic algorithms. From a theoretical point of view, most of the algorithms are very simple and sometimes even trivial. However, the task of designing efficient implementation on a fixed-connection network, such as on FPGA where resources are very limited, has been more demanding, and sometimes quite tedious. Our approach to combat the high power consumption in FSBM motion estimation is based on eliminating unnecessary computation using conservative approximation. Finding a macro block with the minimum distortion is typically a sequential process. Our approach computes a conservative estimate of the exact distortion value for each candidate macro block before computing the exact distortion. If the conservative estimate of the distortion is larger than the minimum distortion found so far, this distortion value is removed from consideration in finding the minimum, i.e., the exact distortion needs not be computed. As long as the power consumed in computing the estimate is negligible, the percentage of skipped distortion computation turns into net power savings. We show that augmenting this conservative approximation technique to conventional systolic architecture based VLSI motion estimation reduces the power consumption by a factor of two, while preserving the optimal solution and the throughput. In summary ,the objective of this paper is twofold:We first describe a full-systolic algorithm for Motion estimation that realizes the real-time coding; to achieve the lower power, we introduce a novel circuit that build in the level of algorithm.