Realization And Optimization Of MPEG-4 Video Decoder Based On SOC

With the fast development of digital technology, kinds of mobile equipments areaccepted bypeople. Video player is integrated by more and more mobileproducts。Withthe advantage of coding technique and compressing ability,MPEG-4 is becoming mostpopularvideofomat.MPEG-4playerhasagreatperspective asahandhold product.But the mass of computation give a lot of pressure on the processor of embeddedequipment whose use ARM7 as a core. Software decoding always can't meet therequirement of real time play. The purpose of this paper is that, design a hardwareaccelerator-MMA,fortheGarfieldSOCtohelpinMPEG-4CIFdecoding.In order to know the performance of MPEG-4 decoding precisely, we run softwaredecoding program on the high level hardware model ARMulator first. By analysis theresult, we get the profile of everyoperation of MPEG-4 decoding, which indicatesIDCT,VLC decoding and motion compensation occupy the most CPU resources. So, theseoperations are the important parts of hardware acceleration. With every operation, thepaper firstly optimizes the algorithm, then decides the hardware construction and thendesignsthecircuitdetails.Finally,thepapergivesout theperformanceandareaofMMA.The result indicate that this MPEG-4 video decoder meet the requirement of MPEG-4CIFformatrealtimedecoding.At last, the paper gives out the research directions of some other multimediastructure,includingARMcoreplusDSPstructure.