The FPGA Implementation Research Of The Decoding On Turbo Product Code

In communication, researchers are always devoted to study on efficiency and reliability. In 1994, P.Ryndiah investigates Turbo Product Code. It is a kind of block code, of which sub-code is linear code. Its decoding method adopts SISO iterative, the same as Turbo code, so called Turbo Product Code. TPC has nearly the same performance as Turbo code, especially simpler decoding method. So, it becomes the focus of the coding area, and will be widely applied in high speed communication.In this paper, the coding and decoding principle of TPC is firstly researched. The contents of coding section are that two or more than two linear sub-codes form a code block, and then each dimension is coded separately. These sub-codes can be the same or not, BCH code, single parity check code, extended Hamming code, and so on.The whole realization scheme of TPC decoding based on FPGA, design flow and unit decoder are discussed in detail, of which sub-code is (64,57) Extended Hamming code. The hardware description language and IDE adopted are Verilog HDL and QuartusII-5.0.The decoder is compiled and simulated in EP1C12Q240C by QuartusII-5.0. The different error style is added to the sequence received in emulated channel. Correspondingly, the correct decoding results are attained at the output terminal. After the resource and decoding speed are optimized, the work clock can be achieved at 50MHz, and serial decoding speed is high to 2.4Mbps. It can satisfy the requirement of base band data transfer. Furthermore, some other available decoding arithmetic are compared, for seeking better decoding performance in the future.