Reverse Design Of TL16C554 Chip

The design level of our country integrated circuit is still very low. The design of the correspondence chip too is such. The microelectronics technique and intelligence computer aided design technique that reform electronics product has been a kind of inevitable trend. The tool of EDA design in integrated circuit the technique occupied in work development with deal more and more high, the chip design item is also depended on increasingly in the system of EDA with advanced design method.The TL16C554 Asynchronous Communications Element (ACE) chip item is from Chinese electronics technology group company the 47th graduate school design room develop the large scale integrated circuit in a piece of the digital CMOS. It is enhanced quadruple versions of the TL16C550 ACE. Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The completed status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered. The TL16C554 can be placed in an alternate FIFO mode, which activates the internal FIFO to allow 16 bytes to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216-1). Independently controlled transmit, receive, line status, and data set interrupts. The thesis inside was detailed to discuss the TL16C554 work principle. It is also detailed to introduce every kind of circuit type met in the TL16C554 circuit analysis and design, and the basic thought of analysis design of cycle time circuit.